ADF 4001 BRUZ – Phasenregler, PPL, 10 … 200 MHz, TSSOP-16

The ADF4001 clock generator can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, and a programmable 13-bit N counter. In addition, the 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator) or VCXO (voltage controlled crystal oscillator). The N minimum value of 1 allows flexibility in clock generation. 200 MHz Bandwidth 2.7 V to 5.5 V Power Supply Programmable Charge Pump Currents 3-Wire Serial Interface Hardware and Software Power-Down Mode Analog and Digital Lock Detect